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| author | Eduardo Julian | 2022-01-18 00:20:50 -0400 |
|---|---|---|
| committer | Eduardo Julian | 2022-01-18 00:20:50 -0400 |
| commit | fc854233d2af07ed44a063a75a6900cc02616c74 (patch) | |
| tree | a62ce49314d2101cd77112eee54081153448836e /documentation/bookmark/hardware | |
| parent | e1af5374ba4d969f866867db47af7ecf60cc9933 (diff) | |
Fixes for the pure-Lux JVM compiler machinery. [Part 7]
Diffstat (limited to 'documentation/bookmark/hardware')
| -rw-r--r-- | documentation/bookmark/hardware/fpga.md | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/documentation/bookmark/hardware/fpga.md b/documentation/bookmark/hardware/fpga.md new file mode 100644 index 000000000..8dce079ca --- /dev/null +++ b/documentation/bookmark/hardware/fpga.md @@ -0,0 +1,4 @@ +# Reference + +0. [C++20 on Xilinx FPGA with SYCL for Vitis - Ronan Keryell - CppCon 2021](https://www.youtube.com/watch?v=BJBDmQJdDpc) + |