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| author | Eduardo Julian | 2022-08-14 21:02:22 -0400 |
|---|---|---|
| committer | Eduardo Julian | 2022-08-14 21:02:22 -0400 |
| commit | 0f9bc13a34b729d9ae9db31276feb2a66785d06b (patch) | |
| tree | 25f8ec214bfe56f7dc7d8be637b06d1ab6a425f6 /documentation/bookmark/hardware/fpga__field_programmable_gate_array.md | |
| parent | 24e4ccef052816f17ccfc55f2e515a07cc9c2067 (diff) | |
Documentation changes for v0.7.0
Diffstat (limited to 'documentation/bookmark/hardware/fpga__field_programmable_gate_array.md')
| -rw-r--r-- | documentation/bookmark/hardware/fpga__field_programmable_gate_array.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/documentation/bookmark/hardware/fpga__field_programmable_gate_array.md b/documentation/bookmark/hardware/fpga__field_programmable_gate_array.md new file mode 100644 index 000000000..e66984228 --- /dev/null +++ b/documentation/bookmark/hardware/fpga__field_programmable_gate_array.md @@ -0,0 +1,6 @@ +# Reference + +0. []() +0. [Parallel Programming for FPGAs](https://kastner.ucsd.edu/hlsbook/) +0. [C++20 on Xilinx FPGA with SYCL for Vitis - Ronan Keryell - CppCon 2021](https://www.youtube.com/watch?v=BJBDmQJdDpc) + |