diff options
| author | Cheng-Han, Wu | 2016-04-20 18:11:40 +0800 |
|---|---|---|
| committer | Cheng-Han, Wu | 2016-04-20 18:11:40 +0800 |
| commit | 8bf516263c6582771e7576e8484ca8cfaa8cb9cb (patch) | |
| tree | aba81172f554a50466a762db99f25e3650d7ff45 /public/vendor/codemirror/mode/verilog/index.html | |
| parent | edc3a31dfdb03e910d7355144280e281eeb582d5 (diff) | |
Update CodeMirror to 5.13.5
Diffstat (limited to 'public/vendor/codemirror/mode/verilog/index.html')
| -rw-r--r-- | public/vendor/codemirror/mode/verilog/index.html | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/public/vendor/codemirror/mode/verilog/index.html b/public/vendor/codemirror/mode/verilog/index.html index 96b3d647..9c52722a 100644 --- a/public/vendor/codemirror/mode/verilog/index.html +++ b/public/vendor/codemirror/mode/verilog/index.html @@ -112,7 +112,7 @@ endclass Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800). <h2>Configuration options:</h2> <ul> - <li><strong>noIndentKeywords</strong> - List of keywords which should not cause identation to increase. E.g. ["package", "module"]. Default: None</li> + <li><strong>noIndentKeywords</strong> - List of keywords which should not cause indentation to increase. E.g. ["package", "module"]. Default: None</li> </ul> </p> |