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| author | Wu Cheng-Han | 2015-05-04 15:53:29 +0800 |
|---|---|---|
| committer | Wu Cheng-Han | 2015-05-04 15:53:29 +0800 |
| commit | 4b0ca55eb79e963523eb6c8197825e9e8ae904e2 (patch) | |
| tree | 574f3923af77b37b41dbf1b00bcd7827ef724a28 /public/vendor/codemirror/mode/verilog/index.html | |
| parent | 61eb11d23c65c9e5c493c67d055f785cbec139e2 (diff) | |
First commit, version 0.2.7
Diffstat (limited to 'public/vendor/codemirror/mode/verilog/index.html')
| -rwxr-xr-x | public/vendor/codemirror/mode/verilog/index.html | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/public/vendor/codemirror/mode/verilog/index.html b/public/vendor/codemirror/mode/verilog/index.html new file mode 100755 index 00000000..96b3d647 --- /dev/null +++ b/public/vendor/codemirror/mode/verilog/index.html @@ -0,0 +1,120 @@ +<!doctype html> + +<title>CodeMirror: Verilog/SystemVerilog mode</title> +<meta charset="utf-8"/> +<link rel=stylesheet href="../../doc/docs.css"> + +<link rel="stylesheet" href="../../lib/codemirror.css"> +<script src="../../lib/codemirror.js"></script> +<script src="../../addon/edit/matchbrackets.js"></script> +<script src="verilog.js"></script> +<style type="text/css">.CodeMirror {border-top: 1px solid black; border-bottom: 1px solid black;}</style> +<div id=nav> + <a href="http://codemirror.net"><h1>CodeMirror</h1><img id=logo src="../../doc/logo.png"></a> + + <ul> + <li><a href="../../index.html">Home</a> + <li><a href="../../doc/manual.html">Manual</a> + <li><a href="https://github.com/codemirror/codemirror">Code</a> + </ul> + <ul> + <li><a href="../index.html">Language modes</a> + <li><a class=active href="#">Verilog/SystemVerilog</a> + </ul> +</div> + +<article> +<h2>SystemVerilog mode</h2> + +<div><textarea id="code" name="code"> +// Literals +1'b0 +1'bx +1'bz +16'hDC78 +'hdeadbeef +'b0011xxzz +1234 +32'd5678 +3.4e6 +-128.7 + +// Macro definition +`define BUS_WIDTH = 8; + +// Module definition +module block( + input clk, + input rst_n, + input [`BUS_WIDTH-1:0] data_in, + output [`BUS_WIDTH-1:0] data_out +); + + always @(posedge clk or negedge rst_n) begin + + if (~rst_n) begin + data_out <= 8'b0; + end else begin + data_out <= data_in; + end + + if (~rst_n) + data_out <= 8'b0; + else + data_out <= data_in; + + if (~rst_n) + begin + data_out <= 8'b0; + end + else + begin + data_out <= data_in; + end + + end + +endmodule + +// Class definition +class test; + + /** + * Sum two integers + */ + function int sum(int a, int b); + int result = a + b; + string msg = $sformatf("%d + %d = %d", a, b, result); + $display(msg); + return result; + endfunction + + task delay(int num_cycles); + repeat(num_cycles) #1; + endtask + +endclass + +</textarea></div> + +<script> + var editor = CodeMirror.fromTextArea(document.getElementById("code"), { + lineNumbers: true, + matchBrackets: true, + mode: { + name: "verilog", + noIndentKeywords: ["package"] + } + }); +</script> + +<p> +Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800). +<h2>Configuration options:</h2> + <ul> + <li><strong>noIndentKeywords</strong> - List of keywords which should not cause identation to increase. E.g. ["package", "module"]. Default: None</li> + </ul> +</p> + +<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> and <code>text/x-systemverilog</code>.</p> +</article> |