From 0d909187d5b9effcd08f533d50af7d29c0d6bfd8 Mon Sep 17 00:00:00 2001
From: Eduardo Julian
Date: Fri, 8 Apr 2022 05:42:36 -0400
Subject: De-sigil-ification: $

---
 .../compositor/generation/primitive.lux            | 34 +++++++++++-----------
 1 file changed, 17 insertions(+), 17 deletions(-)

(limited to 'stdlib/source/specification/compositor/generation/primitive.lux')

diff --git a/stdlib/source/specification/compositor/generation/primitive.lux b/stdlib/source/specification/compositor/generation/primitive.lux
index db50dc185..46ba10d00 100644
--- a/stdlib/source/specification/compositor/generation/primitive.lux
+++ b/stdlib/source/specification/compositor/generation/primitive.lux
@@ -28,22 +28,22 @@
 
 (def: .public (spec run)
   (-> Runner Test)
-  (`` ($_ _.and
-          (~~ (template [<evaluation_name> <synthesis> <gen> <test>]
-                [(do r.monad
-                   [expected <gen>]
-                   (_.test (%.symbol (symbol <synthesis>))
-                           (|> (run <evaluation_name> (<synthesis> expected))
-                               (pipe.case
-                                 {try.#Success actual}
-                                 (<test> expected (as_expected actual))
+  (`` (all _.and
+           (~~ (template [<evaluation_name> <synthesis> <gen> <test>]
+                 [(do r.monad
+                    [expected <gen>]
+                    (_.test (%.symbol (symbol <synthesis>))
+                            (|> (run <evaluation_name> (<synthesis> expected))
+                                (pipe.case
+                                  {try.#Success actual}
+                                  (<test> expected (as_expected actual))
 
-                                 {try.#Failure _}
-                                 false))))]
+                                  {try.#Failure _}
+                                  false))))]
 
-                ["bit" synthesis.bit  r.bit  bit#=]
-                ["i64" synthesis.i64  r.i64  "lux i64 ="]
-                ["f64" synthesis.f64  r.frac  f.=']
-                ["text" synthesis.text (r.ascii 5) text#=]
-                ))
-          )))
+                 ["bit" synthesis.bit  r.bit  bit#=]
+                 ["i64" synthesis.i64  r.i64  "lux i64 ="]
+                 ["f64" synthesis.f64  r.frac  f.=']
+                 ["text" synthesis.text (r.ascii 5) text#=]
+                 ))
+           )))
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