From fc854233d2af07ed44a063a75a6900cc02616c74 Mon Sep 17 00:00:00 2001
From: Eduardo Julian
Date: Tue, 18 Jan 2022 00:20:50 -0400
Subject: Fixes for the pure-Lux JVM compiler machinery. [Part 7]

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 documentation/bookmark/hardware/fpga.md | 4 ++++
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 create mode 100644 documentation/bookmark/hardware/fpga.md

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+# Reference
+
+0. [C++20 on Xilinx FPGA with SYCL for Vitis - Ronan Keryell - CppCon 2021](https://www.youtube.com/watch?v=BJBDmQJdDpc)
+
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